Cisco chip exec sees steady ASIC investments
“Our investments [in ASICs] have been and continue to be large,” said Dan Lenoski who manages a team of about 125 of Cisco’s 750 chip designers. “That investment has been steady and increased since in 2000 because communications interfaces are getting faster,” Lenoski explained.
The raw number of ASIC designs may have declined over the years due to greater silicon integration, said Lenoski. Still, Cisco launches as many as several dozen new ASIC programs annually. It is widely regarded as one of the world’s largest ASIC developers and hosts its own annual “Chips at Cisco” conference for its engineers.
“The future in our mind is clearly [about] continued investment,” said Lenoski. “We do see merchant silicon sometimes filling our needs, but we can’t do packet processing and forwarding at the rates we want to hit and control our destiny without our own silicon.”
For example, Lenoski’s team, which designs chips for Cisco’s data center group, recently announced Monticello, a 40-nm chip that powers the company’s Nexus 3548 switch. The 412-mm2 chip packs 2.5 billion transistors delivering 48 ports of 10 Gbit/second Ethernet with 250-nanosecond latency in standard mode and as little as 50 nanoseconds in a dedicated mode. The latter is geared to Wall Street’s high-frequency traders and other speed demons
“We had never fully optimized for latency before, so we looked at everything from packet processing to queuing and output on a single chip with shared memory doing cut-through switching,” said Lenoski. “We have a number of experts in networking, silicon and the customer applications, and it’s the combination of that knowledge that lets us do these things,” he said.
The near-GHz chip is one of several 40-nm designs now in shipping Cisco products. “We have a number of 28-nm designs in the pipeline, but we are not in a lot of production at 28 nm yet,” Lenoski said.
The company’s ASICs serve a range of systems including high-end, processor-intensive routers and boxes that push the limits of virtual switching or pack an outsized number of 40- and 100-Gbit/s interfaces.
Proponents of the OpenFlow initiative said the trend toward centralized software-defined networks will radically simplify the tomorrow’s routers and switches. Lenoski doesn’t buy that.
“There are real-time constraints and reachability issues because switches and routers are distributed, deployed all over the place, and they are not one-to-one connected to servers,” Lenoski said. “So I think a lot of functions will stay in switches and routers, but the ability to program and understand the network [centrally] will increase over time,” he added.
Intel may be Cisco’s foundry
Intel is talking to Cisco about becoming its foundry, says investment bank Piper Jaffray.
According to the bankers, the deal could be worth $1 Billion a year to Intel.
Cisco would be Intel’s fourth announced foundry partner but by far the biggest. The other three announced partners, and there are said to be other unannounced partners, are Achronix, Tabula and Netronome.
Netronome is a network processor company from Santa Clara, California Intel’s home town, with whom Intel has been working for five years on development but onlt signed up for foundry services earlier this year. Under the agreement, Netronome also gets to use Intel’s own EDA tools.
Achronix and Tabula are FPGA companies. Achronix was the first, signing up for Intel foundry in 2010.